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Description

Features :

1. High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX architecture

2. 3.3-V in-system programmability(ISP) through the built–in IEEE Std. 1149.1 Joint Test ActionGroup (JTAG) interface with advanced pin-locking capability
(1) ISP circuitry compliant with IEEE Std. 1532

3. Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990

4. Enhanced ISP features:
(1) Enhanced ISP algorithm for faster programming
(2) ISP_Done bit to ensure complete programming
(3) Pull-up resistor on I/O pinsduring in–system programming

5. High–density PLDs ranging from 600 to 10,000 usable gates

6. 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz

7. MultiVolt I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels