– 16-BIT CPU WITH 4-STAGE PIPELINE – 50ns INSTRUCTION CYCLE TIME AT 40MHz MAX CPU CLOCK – MULTIPLY/ACCUMULATE UNIT (MAC) 16 x 16-BIT MULTIPLICATION – REPEAT UNIT – ENHANCED BOOLEAN BIT MANIPULATION FA CILITIES – ADDITIONAL INSTRUCTIONS TO SUPPORT HLL AND OPERATING SYSTEMS – SINGLE-CYCLE CONTEXT SWITCHING SUPPORT