PDF WMF512K8-XCLX5 Download

Description

1. Access Times of 60, 70, 90, 120, 150ns
2. 100,000 Erase/Program Cycles Minimum
3. 2.5V I/O (SSTL_2 compatible)
4. Sector Erase Architecture
5. 8 equal size sectors of 64K bytes each
6. Any combination of sectors can be concurrently erased. Also supports full chip erase
7. Organized as 512Kx8
8. Commercial, Industrial and Military Temperature Ranges
9. 5 Volt Programming
10. Low Power CMOS
11. Embedded Erase and Program Algorithms
12. TTL Compatible Inputs and CMOS Outputs
13. Page Program Operation and Internal Program Control Time.
 

Description

1. Access Times of 60, 70, 90, 120, 150ns
2. 100,000 Erase/Program Cycles Minimum
3. 2.5V I/O (SSTL_2 compatible)
4. Sector Erase Architecture
5. 8 equal size sectors of 64K bytes each
6. Any combination of sectors can be concurrently erased. Also supports full chip erase
7. Organized as 512Kx8
8. Commercial, Industrial and Military Temperature Ranges
9. 5 Volt Programming
10. Low Power CMOS
11. Embedded Erase and Program Algorithms
12. TTL Compatible Inputs and CMOS Outputs
13. Page Program Operation and Internal Program Control Time.