Description:
1. Access Times of 50*, 60, 70, 90, 120, 150ns
2. Packaging: 32 pin, Rectangular Ceramic Leadless Chip Carrier (Package 601)
3. 100,000 Erase/Program Cycles Minimum
4. 2.5V I/O (SSTL_2 compatible)
5. Sector Erase Architecture
6. 8 equal size sectors of 16KBytes each
7. Any combination of sectors can be concurrently erased. Also supports full chip erase
8. Organized as 128Kx8
9. Commercial, Industrial and Military Temperature Ranges
10. 5 Volt Programming
11. Low Power CMOS
12. Embedded Erase and Program Algorithms
13. TTL Compatible Inputs and CMOS Outputs
14. Page Program Operation and Internal Program Control Time.
15. The access time of 50ns is available in industrial and commercial temperature ranges only.
Description:
1. Access Times of 50*, 60, 70, 90, 120, 150ns
2. Packaging: 32 pin, Rectangular Ceramic Leadless Chip Carrier (Package 601)
3. 100,000 Erase/Program Cycles Minimum
4. 2.5V I/O (SSTL_2 compatible)
5. Sector Erase Architecture
6. 8 equal size sectors of 16KBytes each
7. Any combination of sectors can be concurrently erased. Also supports full chip erase
8. Organized as 128Kx8
9. Commercial, Industrial and Military Temperature Ranges
10. 5 Volt Programming
11. Low Power CMOS
12. Embedded Erase and Program Algorithms
13. TTL Compatible Inputs and CMOS Outputs
14. Page Program Operation and Internal Program Control Time.
15. The access time of 50ns is available in industrial and commercial temperature ranges only.
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