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Description

The device is a single-chip PLL frequency synthesizer designed for TV and VCR tuning systems.

The circuit consists of a divide-by-eight prescaler with its own preamplifier, a 15-bit programmable divider, a crystal oscillator and its programmable reference divider and a phase/frequency detector combined with a charge-pump which drives the tuning amplifier and the 33 V output.

Four high-current PNP band switch buffers are provided for band switching. Two PNP buffers can be switched on simultaneously. The sum of the collector currents is limited to 50 mA.

Block Diagram 

Features

1. Complete 1.3 GHz single chip system

2. Four PNP band switch buffers (40 mA)

3. 33 V output tuning voltage

4. In-lock detector

5. 15-bit programmable divider

6. Programmable reference divider ratio (512, 640 or 1024)

7. Programmable charge-pump current (60 or 280 mA)