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Description

The SSTV16857 is a 14-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. VDDQ must not exceed VCC. Inputs are SSTL_2 type with VREFnormally at 0.5*VDDQ. The outputs support class I which can be used for
standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTV16857 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus
bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTV16857 is intended to be used for SSTL_2 input and output signals.

Features

• Stub-series terminated logic for 2.5 V VDDQ(SSTL_2)
• Optimized for DDR (Double Data Rate) SDRAM applications
• Inputs compatible with JESD8–9 SSTL_2 specifications.
• Flow-through architecture optimizes PCB layout
• ESD classification testing is done to JEDEC Standard JESD22.
• Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA.
• Same form, fit, and function as SSTL16877
• Full DDR 200/266 solution @ 2.5 V when used with PCKV857
• See SSTV16856 for driver/buffer version with mode select.
• Available in TSSOP-48, TVSOP-48 and 56 ball VFBGA packages