Description:This is a single 2-input positive-NAND gate that is designed in Texas Instrument’s ultra-low power technology. It performs the Boolean function Y = A × B or Y = A + B in positive logic. The AUP family of devices has quiescent power consumption less than 1 µA and comes in the ultra small DPW package. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm. Features • Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch • Low Static-Power Consumption • Low Dynamic-Power Consumption • Optimized for 3.3-V Operation |
Related Part Number |
SNJ54HCT652JT | SNC109 SN8P2613 | SN8P2602B SN8P2501 | SN75ALS199N |