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Description

These 11-bit buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1or OE2) input is high, all 11 outputs are in the high-impedance state. These devices provide inverted data.

Features

1. Output Ports Have Equivalent 25-W Series Resistors, So No External Resistors Are

Required

2. State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation

3. Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17