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Description

The SN65LVDS311 serializer transmits 27 parallel input data over 1, 2, or 3 serial output links. The device pinout is optimized to interface with the OMAP3630 application processor. The device loads a shift register with the 24 pixel bits and 3 control bits from the parallel CMOS input interface. The data are latched into the device by the pixel clock, PCLK. In addition to the 27 bits, the device adds a parity bit and two reserved bits for a total number of 30 serial bits. The parity bit allows a receiver to detect single bit errors. Odd parity is implemented. The serial shift register is uploaded through 1, 2, or 3 serial outputs at 30, 15, or 10 times the pixel clock data rate. A copy of the pixel clock is output on an additional differential output. The serial data and clock are transmitted via Sub Low-Voltage Differential Signaling (SubLVDS) lines. The SN65LVDS311 supports three power modes (Shutdown, Standby and Active) to conserve power.

Features

• 2.8 × 2.8mm package size
• 1.8V input signal swing
• 24-Bit RGB Data, 3 Control Bits, 1 Parity Bit and 2 Reserved Bits Transmitted over 1, 2 or 3 Differential Lines
• SubLVDS Differential Voltage Levels
• Three Operating Modes to Conserve Power
– Active-Mode QVGA 17.4mW (typ)
– Active-Mode VGA 28.8mW (typ)
– Shutdown Mode ≈ 0.5μA (typ)
– Standby Mode ≈ 0.5μA (typ)
• ESD Rating > 3kV (HBM)
• Pixel Clock Range of 4MHz–65MHz
• Failsafe on all CMOS Inputs
• Typical Application: Cameras, Embedded Computers

Official Homepage : https://www.ti.com/product/SN65LVDS311