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Description

The PSD family of memory systems for microcontrollers brings In-System-Programmability 
(ISP) to Flash memory and programmable logic.

The result is a simple and flexible solution for embedded designs. PSD devices combine many of
the peripheral functions found in MCU based applications.

The CPLD in the PSD devices features an optimized macrocell logic architecture. The PSD mac
rocell was created to address the unique requirements of embedded system designs. It al
lows direct connection between the system address/data bus, and the internal PSD registers, to
simplify communication between the MCU and other supporting devices.

Features

1. Flash In-System Programmable (ISP) Peripheral for 8-bit MCUs
2. 3.3 V±10% Single Supply Voltage
3. 2 Mbit of Primary Flash Memory (8 uniform sectors, 32K x 8)
4. 256 Kbit Secondary Flash Memory (4 uniform sectors)
5. 64 Kbit of battery-backed SRAM
6. Over 3,000 Gates of PLD: DPLD and CPLD
7. 27 Reconfigurable I/O ports
8. Enhanced JTAG Serial Port
9. Programmable power management
10. High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory
– 1,000 Erase/Write Cycles of PLD