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Description

The NPIC6C596A-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MRinput. A LOW on MRresets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input.

The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. Ifboth clocks are connected together, the shift register is always one clock pulse ahead of the storage register. To provide additional hold time in cascaded applications, the serial output QS7 is clocked out onthe falling edge of SHCP. Data in the storage register drives the gate of the outputextended-drain NMOS (EDNMOS) transistor whenever the output enable input (OE) is LOW.

Features

• Wide supply range 2.3 V to 5.5 V

• Low RDSon

• Eight Power EDNMOS transistor outputs of 100 mA continuous current

• 250 mA current limit capability

• Output clamping voltage 33 V

• 30 mJ avalanche energy capability

• Enhanced cascading for multiple stages

• All registers cleared with single input

Description

The NPIC6C596A-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MRinput. A LOW on MRresets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input.

The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. Ifboth clocks are connected together, the shift register is always one clock pulse ahead of the storage register. To provide additional hold time in cascaded applications, the serial output QS7 is clocked out onthe falling edge of SHCP. Data in the storage register drives the gate of the outputextended-drain NMOS (EDNMOS) transistor whenever the output enable input (OE) is LOW.

Features

• Wide supply range 2.3 V to 5.5 V

• Low RDSon

• Eight Power EDNMOS transistor outputs of 100 mA continuous current

• 250 mA current limit capability

• Output clamping voltage 33 V

• 30 mJ avalanche energy capability

• Enhanced cascading for multiple stages

• All registers cleared with single input