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Description

1. High-performance, E2CMOS 3.3-V & 5-V CPLD families
2. Flexible architecture for rapid logic designs
    — Excellent First-Time-FitTM and refit feature
    — SpeedLocking performance for guaranteed fixed timing
    — Central, input and output switch matrices for 100% routability and 100% pin-out retention
3.  High speed
    — 5.0ns tPD Commercial and 7.5ns tPD Industrial
    — 182MHz fCNT
4. 32 to 512 macrocells; 32 to 768 registers
5. 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
6.  Flexible architecture for a wide range of design styles