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Description

1. High-performance, E2CMOS 3.3-V & 5-V CPLD families
2. Flexible architecture for rapid logic designs
    - Excellent First-Time-FitTM and refit feature
    - SpeedLocking performance for guaranteed fixed timing
    - Central, input and output switch matrices for 100% routability and 100% pin-out retention
3. High speed
    - 7.5ns tPD Commercial and 10ns tPD Industrial
    - 111.1MHz fCNT
4. 32 to 256 macrocells; 32 to 384 registers
5. 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
6. Flexible architecture for a wide range of design styles
    - D/T registers and latches
    - Synchronous or asynchronous mode
    - Dedicated input registers
    - Programmable polarity
    - Reset/ preset swapping