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Description

The ADSP-218xN, ADSP-2184N series consists of six single chip microcomputers optimized for digital signal processing applications. The high-level block diagram for the ADSP-218xN series members appears on the previous page. All series members are pin-compatible and are differentiated solely by the amount of on-chip SRAM. This feature, combined with ADSP-21xx code compatibility, provides a great deal of flexibility in the design decision.

Features

1. 12.5 ns Instruction cycle time @1.8 V (internal), 80 MIPS sustained performance
2. Single-cycle instruction execution
3. Single-cycle context switch
4. 3-bus architecture allows dual operand fetches in every 
5. Multifunction instructions
6. Power-down mode featuring low CMOS standby power dissipation with 200 CLKIN cycle recovery from power-down condition
7. Low power dissipation in idle mode