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Description

The AD6643 is an 11-bit, 200 MSPS/250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired. The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC
clock duty cycle, allowing the converters to maintain excellent performance.

Features

1. 11-bit, 250 MSPS output data rate per channel
2. Total power consumption: 706 mW at 200 MSPS
3. 1.8 V supply voltages
4. LVDS (ANSI-644 levels) outputs
5. Integer 1-to-8 input clock divider (625 MHz maximum input)
6. Internal ADC voltage reference
7. Flexible analog input range
8. 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
9. Differential analog inputs with 400 MHz bandwidth
10. 95 dB channel isolation/crosstalk
11. Serial port control
12. Energy saving power-down modes

Applications 

1. Communications
2. Diversity radio and smart antenna (MIMO) systems
3. Multimode digital receivers (3G)
4. WCDMA, LTE, CDMA2000
5. WiMAX, TD-SCDMA
6. I/Q demodulation systems
7. General-purpose software radios