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Description

A3V56S30FTP is organized as 4-bank x 8,388,608-word x 8-bit Synchronous DRAM with LVTTL interface and A3V56S40FTP is organized as 4-bank x 4,194,304-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.

A3V56S30FTP and A3V56S40FTP achieve very high speed data rates up to 166MHz, and are suitable for main memories or graphic memories in computer systems.

Features

1. Fully synchronous operation referenced to clock rising edge

2. 4-bank operation controlled by BA0, BA1 (Bank Address)

3. /CAS latency- 2/3 (programmable)

4. Burst length- 1/2/4/8/FP (programmable)

5. Burst type- Sequential and interleave burst (programmable)

6. Byte Control- DQM (A3V56S30FTP), DQML and DQMU (A3V56S40FTP)

7. Random column access

8. Auto precharge / All bank precharge controlled by A10