PDF 74ALS651 Download

Description

The 74LAS651 and 74ALS652 transceivers/registers consist of bus transceiver circuits with 3-State outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers.

Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes High. Output enable (OEAB, OEBA) and select (SAB, SBA) pins are provided for bus management. The 74LAS651-1 and 74ALS652-1 will sink 48mA if the VCCis limited to 5.0V ±0.25V.

Features

• Independent registers for A and B buses

• Multiplexed real-time and stored data

• Choice of non-inverting and inverting data paths

• 3-State outputs