Function : 28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver
Maker : Texas Instruments
The SN74SSQEC32882 implements different power saving mechanisms to reduce thermal power dissipation and to support system power down states. By disabling unused outputs the power consumption is further reduced.
The package is optimized to support high density DIMMs. By aligning input and output positions towards DIMM finger signal ordering and SDRAM ballout the device de-scrambles the DIMM traces allowing low cross talk design with low interconnect latency.
Edge controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs.
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Others datasheet of same file : EC32882S,SN74SSQEC32882,SN74SSQEC32882ZALR