Part Number : SN74SSQEC32882

Function : 28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver

Package : NFBGA 176 Pin Type

Maker : Texas Instruments

Pinouts :
SN74SSQEC32882 datasheet

Description :

The SN74SSQEC32882 implements different power saving mechanisms to reduce thermal power dissipation and to support system power down states. By disabling unused outputs the power consumption is further reduced.

The package is optimized to support high density DIMMs. By aligning input and output positions towards DIMM finger signal ordering and SDRAM ballout the device de-scrambles the DIMM traces allowing low cross talk design with low interconnect latency.

Edge controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs.

Features

1. 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs

2. CKE Powerdown Mode for Optimized System Power Consumption

3. 1.5V/1.35V/1.25V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distributing to Four Differential Outputs

4. 1.5V/1.35V/1.25V CMOS Inputs

5. Checks Parity on Command and Address (CS-Gated) Data Inputs

6. Configurable Driver Strength

Official Homepage : https://www.ti.com/product/SN74SSQEC32882


Datasheet PDF Download :
SN74SSQEC32882 pdf

Others datasheet of same file :

EC32882S, SN74SSQEC-32882, SN74SSQEC32882ZALR

2021/08/10 12:08 2021/08/10 12:08

Posted