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Part Number : SN65LVDS310
Function : PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
Maker : Texas Instruments

Pinouts :
SN65LVDS310 datasheet

Description :

DESCRIPTION
The SN65LVDS310 receiver deserializes FlatLink 3G-compliant serial input data to 27 parallel data outputs. The SN65LVDS310 receiver contains one shift register to load 30 bits from one serial input and latches the 24 pixel bits and 3 control bits out to the
parallel CMOS outputs after checking the parity bit. If a parity error is detected, the data output bus disregards the newly received pixel. Instead, the last data word is held on the output bus for another clock cycle.

FEATURES
• Serial Interface Technology
• Compatible With FlatLink™ 3G Transmitters
(E.g., SN65LVDS305 or SN65LVDS307)
• Supports Video Interfaces up to 24-Bit RGB
Data and 3 Control Bits Received Over One
SubLVDS Differential Data Line
• SubLVDS Differential Voltage Levels
• Up to 405-Mbps Data Throughput
• Three Operating Modes to Conserve Power
– Active mode QVGA: 17 mW
– Typical Shutdown: 0.7 µW
– Typical Standby Mode: 67 µW Typical
• ESD Rating > 4 kV (HBM)
• Pixel-Clock Range of 4 MHz–15 MHz
• Failsafe on All CMOS Inputs
• Packaged in 4-mm × 4-mm MicroStar Junior™µBGA® With 0,5-mm Ball Pitch
• Very Low EMI

 


Datasheet PDF Download :
SN65LVDS310 pdf

Others datasheet of same file : SN65LVDS310,SN65LVDS310ZQCR,SN65LVDS310ZQCT
2015/01/28 13:52 2015/01/28 13:52

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